This invention relates to the field of semiconductor devices, such as integrated circuits, and their fabrications. More particularly, this invention relates to methods and devices to alleviate degradation of transistors in integrated circuits.
It is well known that metal oxide semiconductor (MOS) transistors in integrated circuits (ICs) undergo performance degradation during operation. P-channel MOS (PMOS) transistors are subject to negative bias temperature instability (NBTI) mechanisms and other PMOS degradation mechanisms, while n-channel MOS (NMOS) transistors are subject to hot carrier mechanisms and other NMOS degradation mechanisms, resulting in reduced on-state current, shifted threshold voltages and increased off-state leakage current. Analog circuits which depend on transistor pairs with closely matched voltage-current relationships may suffer performance loss and possibly malfunction if sufficient degradation shifts occur. Methods of compensating for performance parameter mismatch are frequently limited to initial adjustments, and cannot alleviate subsequent performance shifts.